(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method, and a design layout used, to optimize the yield of dual gate metal oxide semiconductor field effect transistor (MOSFET) devices.
(2) Description of Prior Art
Specific devices designed to provide dual voltage applications, particularly for the deep sub-micron technology, are achieved using two different gate insulator layer thicknesses, sometimes referred to as a dual gate oxide technology. However the process sequences used to form dual gate insulator layers can result in unwanted device leakage phenomena. For example a process used to form two different gate insulator layers entails removal of a first insulator layer, exposing first portions, or active device regions of a semiconductor substrate in which a thin gate insulator layer will be regrown on. Portions of unremoved first insulator layer located on second areas of the semiconductor substrate, now subjected to conditions used to grow the thin gate insulator layer will increase in thickness resulting in a second gate insulator layer located on second portions, or portions of the semiconductor substrate to be used for thicker gate insulator devices, with the second gate insulator layer greater in thickness than the thin gate insulator layer, again located on the thin gate insulator active device portions of the semiconductor substrate.
Although the process sequence described above can be used to obtain two gate insulator thicknesses, several vulnerable situations can be present. First, shallow trench isolation (STI) regions comprised of insulator filled shallow trench shapes is subjected to the process used to remove the first insulator layer. In addition to global recessing of the STI regions, local recessing or notching of the STI region, at the interface of the STI—active device region, can result in regions in which conductive materials used for gate and silicide regions, can be difficult to remove, resulting in gate to substrate leakage or shorts. In addition the dry etch definition of a gate structure, performed exposing the thin gate insulator in the active device region for the devices employing thin gate insulator layers, can result in silicon loss if the thin gate layer is removed during the gate definition procedure, again resulting in unwanted leakages as a result of substrate damage.
The present invention will describe a novel process sequence and mask layout in which the amount of STI area subjected to the process used to clear a subsequent active device region for thin gate insulator formation, is reduced. In addition this invention will describe a novel process sequence and mask layout, in which the amount of thin gate insulator area subjected to the gate structure definition procedure, is reduced. Prior art, such as: Yu et al, in U.S. Pat. No. 6,225,167 B1; Yu, in U.S. Pat. No. 6,171,911 B1; Fang et al, in U.S. Pat. No. 5,668,035; and Chen et al, in U.S. Pat. No. 6,074,915; all describe processes used to form dual gate insulator layers. However these prior arts do not describe the novel mask layout—process sequence combination disclosed in this present invention, in which STI recess and silicon damage is reduced during the process sequence used to fabricate dual gate insulator layers.